design for testability
Ensure Reliable and Robust Chip Designs
This course focuses on Design For Testability (DFT), teaching you how to implement test strategies that improve the manufacturability and reliability of semiconductor devices. Learn key techniques such as scan chains, built-in self-test (BIST), and fault models, essential for ensuring high-quality chip designs in the industry. Perfect for engineers aiming to specialize in testing and verification.
Overview
DFT Course Syllabus
- Why DFT? Need for Testability
- Defects during manufacturing and their effects
- Cost and time impact of testing
- Key DFT concepts: controllability, observability
- DFT Flow in ASIC/SOC Design Lifecycle
- Standards overview: IEEE 1149.1 (JTAG), IEEE 1500, IEEE 1687 (IJTAG)
- Fault modeling and fault simulation
- Stuck-at Faults (SAF): Single stuck-at, multiple stuck-at
- Bridging Faults
- Transition Faults (Delay Faults)
- Path Delay Faults
- Small Delay Defects
- Introduction to fault grading and coverage metrics
- Full Scan, Partial Scan, and Scan Compression
- Multiplexed Scan and Clocked Scan
- Inserting Scan using DFT tools (Synopsys DFT Compiler, Tessent)
- ATPG-friendly RTL Design Guidelines
- Scan Chain Stitching and Validation
- Scan Chain Reordering for Optimization
- Scan Insertion Flow: From RTL to Post Synthesis
- ATPG Flow and Tools
- Fault Simulation and ATPG Pattern Generation
- Stuck-at ATPG
- Transition Delay ATPG
- Test Pattern Compression Techniques
- Advanced ATPG: Embedded Deterministic Test (EDT)
- Test Coverage improvement techniques
- Debugging ATPG failures
- Memory Test Challenges
- MBIST (Memory Built-In Self Test) Concepts
- BIRA (Built-In Redundancy Analysis)
- Implementing MBIST Controllers
- MBIST Insertion, Verification, and Pattern Generation
- Memory Repair Schemes and Algorithms
- Tools like Synopsys STAR Memory System
- IEEE 1149.1 Basics: TAP Controller, Instruction Register, Data Registers
- Bypass Register, IDCODE, EXTEST, INTEST
- Boundary Scan Description Language (BSDL)
- Implementation in SOC
- Board Level Testing with JTAG
- Debugging with JTAG
- Logic BIST (LBIST)
- BIST Architecture and Implementation
- Pattern Generation using PRPG and Response Compaction using MISR
- LBIST vs MBIST: Differences and Applications
- LBIST Insertion, Simulation, and Debug
- Understanding ATPG-based vs BIST-based testing
- Why Test Compression is needed?
- Introduction to Test Compression Architectures
- Input-decompression and Output-compaction
- DFT MAX (Synopsys), Tessent TestKompress (Siemens EDA) flows
- Test Data Volume Reduction Techniques
- Advanced Test Compression (X-Handling, Chain Multiplexing)
- DFT Strategy for multi-core SOCs
- Hierarchical DFT vs Flat DFT
- DFT for IP blocks and integrating into Top Level
- Shared BIST Controllers
- IEEE 1500 - Embedded Core Test
- Setup, Hold, and Slack Analysis in DFT
- Impact of DFT structures on STA
- DFT Clocking Strategy
- Constraints for DFT: Scan Timing Constraints, Test Mode Constraints
- Timing Closure challenges in DFT inserted netlists
- DFT challenges in UPF-based designs
- Scan strategies for Power-Gated Blocks
- Isolation Cells and Retention Flops Handling
- Test during Low Power States
- Power-aware ATPG
- DFT Verification: Scan Checkers, Testability Reports
- Post-DFT Insertion Verification: Formal and Simulation based
- Fault Coverage Analysis
- Pattern Formats: STIL, WGL
- ATE (Automatic Test Equipment) Pattern Formats
- Preparing Final Deliverables for Manufacturing Testing
- Real-life project implementation: Full DFT flow
- Scan Insertion and ATPG for a Small Core
- MBIST implementation on a Multi-port SRAM
- LBIST implementation for a simple CPU block
- Debugging ATPG pattern failure simulations
- Hands-on with Tools: Synopsys DFT Compiler, TetraMAX, Tessent, Cadence Modus
- IEEE 1687 (IJTAG) - Internal JTAG for SOCs
- Advanced Defect Diagnosis
- Test and Diagnosis for FinFET technologies
- Secure DFT: Protecting IP from Scan-based Attacks
DFT (Design for Test) Course Overview
This course is designed to provide hands-on, end-to-end training in DFT techniques, aligned with real-world semiconductor industry standards. Trainees will gain practical knowledge of inserting, simulating, verifying, and analyzing test features such as Scan, ATPG, MBIST, and BIST using industry-leading EDA tools like Synopsys DFT Compiler, TetraMAX, Tessent, Cadence Modus, and STAR Memory System. The course emphasizes DFT in the context of modern SoCs, low power UPF designs, FinFET nodes, and multi-clock domains.
What You'll Learn
- Fundamentals and real need for DFT in IC design
- DFT Flow integration into the ASIC/SoC lifecycle
- Fault models and ATPG techniques
- Scan chain architecture, insertion, and optimization
- Test pattern generation, debugging, and compression
- In-depth memory testing using MBIST and redundancy
- Boundary Scan (IEEE 1149.1) and Advanced iJTAG (IEEE 1687)
- DFT for low power and hierarchical SoC design
- Timing-aware DFT, scan timing constraints, and STA impact
- DFT signoff and pattern delivery for production
Hands-On Tools and Skills
- Toolchains: Synopsys DFT Compiler, TetraMAX, Tessent, STAR Memory System, Cadence Modus
Project Work
- Scan + ATPG for IP with 50k+ scan cells
- MBIST for multi-port SRAMs
- LBIST for simple RISC/CPU core
- DFT in multi-clock SoC with SDC, STA & test patterns
- Debugging ATPG patterns using gate-level simulation
Key Technical Highlights
- Writing SDCs for DFT and test modes
- Gate-level simulation (GLS) with timing & zero-delay
- Real-time debugging of scan/ATPG failures
- Advanced Test Compression architectures (DFT MAX, TestKompress)
- Flat vs Hierarchical DFT trade-offs and real use-cases
- IEEE 1687 (IJTAG): advanced internal test access mechanisms
- On-chip clock generation and control schemes in DFT
Who Should Enroll?
- ASIC Design Engineers transitioning to DFT
- Verification Engineers looking to understand test infrastructure
- Fresh graduates aiming for VLSI careers
- Working professionals seeking to upskill for DFT/ATPG roles
DFT Course Projects
Scan Insertion and ATPG Pattern Generation for a 32-bit ALU-Based IP Block
Full MBIST Implementation for a Dual-Port SRAM Array with Redundancy Repair
Scan Chain Reordering and Optimization for Low Power SoC Design
Hierarchical DFT Implementation and Test Pattern Delivery for a Multi-Core CPU Subsystem
DFT Signoff and GLS Debug for a Mixed-Clock Domain SoC with Clock Domain Crossing (CDC)
On-Chip Clock Controller Design and Integration for Scan Shift and Capture
Boundary Scan (IEEE 1149.1) Insertion and Verification for GPIO and Peripheral Interface Blocks
DFT Insertion and ATPG for Retention and Isolation Enabled Low-Power UPF-Based Design
iJTAG (IEEE 1687) Network Construction and Access Verification for Embedded IP Blocks
LBIST Architecture Design and Simulation for Fault Coverage in a RISC Core
DFT Course – FAQ
- Synopsys DFT Compiler – for scan insertion
- TetraMAX or Tessent – for ATPG
- Cadence Modus – for scan/MBIST
- STAR Memory System – for MBIST flows
- DFT for SoCs with 50k+ scan cells
- MBIST on multi-port memory
- ATPG for multi-clock blocks with debugging
- IEEE 1687 (iJTAG) with practical implementation
- Low Power DFT challenges with UPF-based design handling
- Scan and ATPG in gated/retention blocks
- Writing SDC constraints for DFT modes
- 1:1 mock interviews
- Resume/LinkedIn profile review
- Sample interview questions for DFT/ATPG roles
- Referral assistance based on performance
- DFT Engineer
- ATPG Engineer
- Memory Test Engineer
- SOC Integration Engineer (with DFT focus)
- Post-silicon Test Debug Engineer
Meet Your DFT Expert
A seasoned semiconductor professional with over 10 years of specialized experience in DFT architecture and implementation, dedicated to transforming students into industry-ready DFT engineers.
Professional Journey
At the heart of our DFT course is a trainer whose journey through the semiconductor landscape is nothing short of inspiring. From debugging scan chains at 2 AM in tapeout crunch time to mentoring junior engineers through their first MBIST insertion, his path has been built brick by brick with dedication, technical brilliance, and an unwavering passion for silicon.
With over 10 years of specialized experience in DFT architecture and implementation, he has worked on some of the most complex SoCs in the automotive and consumer domains — seamlessly integrating scan, at-speed, boundary scan, and MBIST strategies to maximize test coverage and silicon reliability.
Industry Impact
He was a key contributor at a global semiconductor product company, where his work helped reduce test cost and power in volume production chips — a challenge only seasoned DFT minds can handle. His expertise spans DFT flow automation, RTL-level test point insertion, ATPG optimization, and ensuring robust design for test logic that meets both area and performance constraints.
Technical Expertise
More importantly, he understands how to navigate the ever-evolving demands of modern chip testing — from safety-critical ISO 26262 designs to ultra-low-power IoT silicon.
Teaching Philosophy
But what truly elevates him beyond his technical credentials is his ability to teach with clarity and empathy. Having mentored over 500+ engineers and interns throughout his career, his teaching is not just about commands or tools — it's about transforming the way students think about design quality and silicon bring-up.
He brings in real scenarios, debug case studies, and post-silicon lessons learned into every session, ensuring students understand not just the 'how,' but also the 'why' behind every step of the DFT flow.
With him as your mentor, you're not just learning DFT — you're gaining a roadmap to becoming a next-generation silicon test architect, ready to take on the industry's toughest challenges with confidence.
COURSE FEE
Course Highlights
• Design and simulate RTL in Verilog
• Master RTL flow from spec to simulation
• Develop and verify FSM systems
• Ace technical interviews with real-world problems