Industry Standard Physical Design
Master the Path from RTL to GDSII in VLSI Engineering
This beginner-level course is tailored to help aspiring VLSI engineers build a strong foundation in Physical Design (PD). Gain hands-on experience with industry-standard tools and processes, including synthesis, floorplanning, placement, routing, and static timing analysis. Learn essential scripting skills in TCL and Linux, preparing you for PD roles in leading semiconductor companies working with SoC, ASIC, and advanced FinFET technologies.
Overview
Physical Design Course Syllabus
- Hands-on training with Linux commands essential for EDA tool usage and automation
- Introduction to TCL (Tool Command Language)
- Writing basic scripts for automation in physical design tools
- Practical exercises for commonly used commands
- Overview of CMOS design principles
- Basic concepts of transistors, gates, and logic design
- Introduction to synthesis and its purpose in physical design
- Synthesis flow overview
- Constraining designs for timing, area, and power
- Understanding timing library (.lib) format
- Hands-on synthesis of a basic design
- Analyzing and debugging synthesis reports
- Basic optimization techniques
- Introduction to timing constraints
- Go through the important timing constraints
- Setting and analyzing constraints for setup and hold timing
- Basic hands-on timing analysis exercises
- Goals of floorplanning
- Basic concepts of area estimation (square/rectangle/rectilinear floorplans)
- IO and macro placement
- Introduction to congestion estimation
- Simple floorplanning exercises with predefined constraints
- Basics of power structure design
- Logical power/ground connections
- Creating and analyzing simple power networks
- Introduction to IR drop analysis
- Hands-on exercise to create power rails and run basic checks
- Goals and types of placement
- Pre-placement: End-cap, tap, and IO buffer cells
- Introduction to standard cell placement
- Basic congestion analysis and reduction techniques
- Hands-on exercises for placement strategies
- Introduction to routing and its types (global, detailed)
- Inputs and outputs of routing
- Basic signal routing tasks
- Congestion checks and RC extraction for net parasitics
- Hands-on exercises for simple routing tasks
- Introduction to static and dynamic power dissipation
- Basics of leakage power analysis
- VT cell swapping for power and timing trade-offs
- Hands-on dynamic power calculation using sample data
- What is CTS and its goals?
- Basics of clock tree structures and specifications
- Setting simple clock constraints such as skew and insertion delay
- Hands-on exercise: Building and analyzing a basic clock tree
- Introduction to ECO and its importance
- Basic types of ECO: Functional and timing
- Flattened ECO flow overview
- Hands-on debugging of simple ECO flows
- Introduction to design rule checks (DRC) and their importance
- Basics of layout vs. schematic (LVS)
- Electrical rule checks and their role
- Static IR drop analysis
- Guided projects covering the complete flow from input files to GDSII, including:
- Synthesis
- Floorplanning
- Power planning
- Placement
- Routing
- Static timing analysis (STA)
- Physical verification (DRC and LVS)
- EDA Tool Familiarization
- Overview of tools such as Synopsys Design Compiler and Cadence Innovus
- Basic navigation and usage
- Low-Power Design Basics
- Introduction to concepts like multi-Vt and power gating
- Simple exercises to understand trade-offs
- Soft Skills for Collaboration
- Guidelines for teamwork in physical design projects
- Best practices for documentation and reporting
- Simple examples integrated into the physical design flow
- Real-World Case Studies
- Beginner-friendly case studies highlighting hierarchical vs. flat design trade-offs
Physical Design Course Overview
This beginner-level Physical Design (PD) course is designed to equip aspiring VLSI engineers with the foundational knowledge and hands-on skills needed to transition from RTL to GDSII. Learners will go through industry-grade PD flow including synthesis, floorplanning, placement, CTS, routing, static timing analysis, power planning, and verification.
Course Highlights
Industry-Grade Flow
- Synthesis
- Floorplanning
- Placement
- CTS
- Routing
- Static Timing Analysis
- Power Planning
- Verification
Practical Skills
- Hands-on Tool Experience
- Real-world Projects
- TCL Scripting
- Linux Environment
Industry Focus
- SoC Design
- ASIC Implementation
- Sub-16nm FinFET Nodes
- Semiconductor Companies
Course Objective
The course integrates hands-on tool experience, real-world projects, and scripting skills in TCL and Linux, making learners job-ready for PD roles in semiconductor companies working on SoC, ASIC, and sub-16nm FinFET nodes.
DFT Course Projects
Scan Insertion and ATPG Pattern Generation for a 32-bit ALU-Based IP Block
Full MBIST Implementation for a Dual-Port SRAM Array with Redundancy Repair
Scan Chain Reordering and Optimization for Low Power SoC Design
Hierarchical DFT Implementation and Test Pattern Delivery for a Multi-Core CPU Subsystem
DFT Signoff and GLS Debug for a Mixed-Clock Domain SoC with Clock Domain Crossing (CDC)
On-Chip Clock Controller Design and Integration for Scan Shift and Capture
Boundary Scan (IEEE 1149.1) Insertion and Verification for GPIO and Peripheral Interface Blocks
DFT Insertion and ATPG for Retention and Isolation Enabled Low-Power UPF-Based Design
iJTAG (IEEE 1687) Network Construction and Access Verification for Embedded IP Blocks
LBIST Architecture Design and Simulation for Fault Coverage in a RISC Core
Welcome to Silicon Valley VLSI Vision Academy
At Silicon Valley VLSI Vision Academy, we believe in delivering more than just training — we offer a gateway into the real semiconductor industry. Our Industry Standard Physical Design course is tailored for aspiring VLSI engineers who are serious about mastering backend design with real-world relevance. From tool access to live projects, we ensure a learning experience that truly stands apart.
🌐 24×7 Cadence Tool Access
We are proud to be the first training institute to provide 24×7 Cadence tool access through a secure VNC setup. Whether you're studying from Dhaka, Delhi, or Dallas, you can log in anytime to explore and practice using the full suite of Cadence Physical Design tools.
💻 Real Industry-Standard Projects
Our course includes three hands-on Physical Design projects, each inspired by real semiconductor industry challenges. These projects cover the entire backend flow — from floorplanning to signoff.
🎓 Cadence Education Platform
In a major industry-first, we provide our students with full access to the Cadence Online Education Platform, typically reserved for corporate and academic institutions.
Tool Mastery with Industry Flow
Throughout the 4-month duration of this course, you will gain hands-on experience with Cadence tools such as Innovus, Genus, Tempus, Voltus, and Quantus. These tools are widely used in today's chip design companies, and you'll follow an industry-aligned physical design flow from RTL to GDSII.
Concept to Industry-Ready Skillset
We start from scratch. Our training begins with clear conceptual foundations, ensuring you understand the physics and architecture behind chip design. From there, we transition into intermediate and advanced tool-based practices that mirror actual backend tapeout workflows.
Why This Course is Unique
Unlike many traditional VLSI coaching centers, we go beyond lectures. We deliver real-time training, industry-aligned tool flows, access to authentic Cadence resources, and personalized mentorship by experts with 10+ years of industry experience.
If your dream is to work in backend design, ASIC layout, or advanced semiconductor development, this course is your launchpad. Learn, practice, and grow under expert guidance — using the exact tools and techniques that power the global chip industry.
Let's shape the future of silicon — together
👉 Join our course today and take the first step toward becoming a certified, job-ready Physical Design Engineer.
What's app us to get more information:
+8801898757546Physical Design Course – FAQ
- Global 24/7 Cadence Tool Access — train anytime, anywhere
- 3 Full Real-World Projects — work hands-on like you're in a semiconductor company
- Official Cadence Education Platform Access — for deeper, certified learning
- Live mentoring + practical flow — not just theory, but RTL to GDSII implementation
- RTL to GDSII implementation for a digital IP block
- Power planning with IR-drop & EM checks
- Clock Tree Synthesis and static timing closure
- Access premium physical design content
- Watch video tutorials by Cadence experts
- Get certified with Cadence badges
- RTL → Synthesis → Floorplanning → Power Planning → Placement → CTS → Routing → STA → Physical Verification
- STA: Setup/hold, slack analysis, timing reports
- ECO Flow: Functional & timing ECOs, netlist patching, and back-annotation
- Multi-Vt design
- Power gating & retention strategies
- Leakage and dynamic power analysis
- You'll have weekly doubt-clearing sessions
- 1:1 mentorship for project reviews, tool guidance, and career advice
- Physical Design Engineer
- ASIC Backend Engineer
- STA Engineer
- PD Verification Engineer
- You'll receive a recognized course completion certificate
- For top-performing students, we offer job referral support to our industry hiring network
- Mock interviews, resume polishing, and placement guidance are included
Meet Your Physical Design Trainer
We are honored to present one of the industry's most experienced and passionate Physical Design engineers as the lead trainer for our Physical Design course — someone whose expertise and mentorship set a benchmark for excellence in VLSI backend design education.
With over a decade of hands-on experience in Physical Design, our trainer has been directly involved in multiple successful chip tape-outs, spanning key domains like Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, and DRC/LVS signoff. His deep understanding of the end-to-end RTL-to-GDSII flow brings unmatched value to every student enrolled in the course.
Previously, he played a foundational role at Ulkasemi, where he helped build and scale the Physical Design team in Bangladesh from the ground up. His contributions were instrumental in establishing Ulkasemi's credibility in the global semiconductor industry. He later moved to a top product-based semiconductor company in Malaysia, where he worked on high-performance and low-power SoC designs, directly contributing to production-grade silicon tape-outs used in commercial electronics.
What truly sets him apart is not just his industry experience, but his dedication to teaching and mentoring. With 10,000+ hours of training experience, he has mentored hundreds of engineers and students across South Asia. Known for his ability to simplify complex backend flows, his sessions are interactive, lab-focused, and industry-aligned. He bridges the gap between academic theory and practical, tool-based design by using real-life case studies, hands-on labs, and project-based learning.
Our trainer believes in cultivating deep problem-solving skills and design intuition in students. Under his mentorship, you won't just learn "what" to do — you'll understand "why" each step matters in a real tape-out scenario. Whether you're a beginner or someone looking to upskill, his guidance will equip you with the mindset and skills of a true industry-grade Physical Design Engineer.
We are proud to have him lead this transformative journey — inspiring the next generation of VLSI engineers to think critically, design smartly, and innovate fearlessly.
Course Highlights
Digital Electronics from Scratch
RTL Design Using Verilog
Complete RTL-to-GDSII Flow
Static Timing Analysis (STA)
Clock Tree Synthesis (CTS)
Power Planning & IR Drop Analysis
Placement, Routing, DRC & LVS Closure
Parasitic Extraction & Noise Analysis
Hands-on Tool Exposure (EDA Flow)
Real-Time Physical Design Projects
SDC Constraints, DEF/LEF/GDSII Formats
Resume Building & Mock Interview Prep